This invention relates generally to testing circuit boards, and more particularly, to testing systems of circuit boards.
The testing of circuit chips and circuit boards is becoming more standardized. For example, the Joint Test Action Group (JTAG) members introduced an IEEE standard 1149.1, Test Access Port and Boundary-Scan Architecture, in 1990. The JTAG standard reduces the need to design a test fixture (e.g., a bed-of-nails tester) to test circuit chip and board functionality.
The test fixture approach includes hardware to connect to the circuit board to be tested. Typically, a bed-of-nails test fixture is attached to the underside of a circuit board with contact points allowing access to test points within the circuit board, including testing of circuit board chips. Through the test fixture, opens and shorts may be produced to test the circuit board functionality. However, the designing and building of separate test fixture hardware to access and test circuit boards and circuit chips may be very expensive (e.g. $100,000 per test fixture). Further, the test fixtures are usually customized to the particular circuit board and chips to be tested, which limits the testing capabilities of the test fixture. Additionally, when modifications to the circuit board and/or chips are made, the existing test fixture may need modification, redesigning or in some cases, building a new test fixture.
The bed-of-nails approach to testing circuit boards has further disadvantages. As circuit chips become smaller, difficulty in accessing the internals of chips and circuit boards has increased. Further, smaller components has lead to the production of very complex chips that are increasingly hard to test with a bed-of-nails approach.
With the development of the JTAG IEEE 1149.1 standard (herein referred to as JTAG), a new approach has evolved. JTAG introduces a boundary-scan approach to testing. A boundary scan determines a boundary defined by, for example, a circuit board or some set of chips on a circuit board, and provides controls, such as observe/control cells that results in a bound internal net of circuitry within the boundary. The observe/control cells provide inputs to the bounded circuitry for observing the response outputs. A boundary scan (BScan) process is used to define a control and observation (e.g. a scan) of a net of circuitry (e.g. digital logic) within a boundary. Using BScan, a bed-of-nails is replaced with virtual nails or boundary scan cells. Further, board/chip manufacturers are building test points (e.g. BScan cells) into silicon chips and circuit boards. A JTAG 4/5-wire interface is often supported on the circuit board to supply a standard test access point (TAP). Essentially the hardware of a bed-of-nails test facility is replaced with software. Additionally, test access is not limited to the main I/O ports of the board, but test access is provided down to a chip I/O (pin) level through the JTAG 4/5 wire interface and the BScan cells.
Thus, the complexity of the chip is less of an issue. Boundary scan essentially partitions digital logic to facilitate control and observation of the functionality of test chip or board. For example, the BScan process partitions boards at chip I/Os for control and observation of board-level nodes. Test generation also requires less manual operation compared to previous testing methods. The BScan process provides a testing method to arbitrarily generate source test stimulus to the net structure and observe test results. The BScan testing of the net structure (e.g., a circuit board or a sub-logic of the circuit board) is independent of the integration complexity of the individual chips.
JTAG boundary scan testing has improved chip and board testing, but most of the JTAG testing is performed by manufacturers and at the chip and board level specific to those certain manufacturers. Further, JTAG testing is typically not performed to test the connectivity of a set of boards and/or a system of interconnected boards (e.g., system level testing).
Thus, JTAG testing is limited to testing of specific components within a system or board.